1. Field
The disclosure relates to integrated circuit design, and, in particular, to techniques for designing amplifiers having a multi-cascode configuration.
2. Background
In the design of CMOS RF power amplifiers (PA's), a multi-cascode circuit topology may be adopted, wherein multiple cascode transistors are provided at the drain of an input transistor. To generate bias voltages for the multi-cascode circuit, a resistive divider from a supply voltage to ground may be tapped and provided to the gates of the multiple cascode transistors, while a separate network may be used to bias the input transistor. One shortcoming of this solution is that the mapping between the bias voltages generated thereby and the desired currents in the devices may not be accurate, as the configuration of the bias networks of the input transistor is different from that of the cascode amplifier circuit.
In a further aspect of amplifier design, a variable attenuation element may be coupled in series with the PA to provide the PA with variable gain. To adjust the power of the PA output, the attenuation provided by the attenuation element may be adjusted. A disadvantage of this approach is that the attenuation element needs to be provided directly in the signal path of the PA, and may thus undesirably contribute to noise in the PA output, and also vary both the input and output impedances of the PA.
It would be desirable to provide accurate and efficient techniques for biasing a multi-cascode amplifier circuit, and further to provide variable gain to such a multi-cascode amplifier circuit without necessarily introducing a series attenuation element into the signal path.